Programmable driver circuits are typically used to drive loads while simultaneously matching the impedance of the loads being driven. Because mismatch between the impedance of a driver circuit and the characteristic impedance of the load is very undesirable in high performance and small signal applications (e.g., SRAM memory device applications), external variable resistors have been used to program the impedance of a driver circuit to match the impedance of the load.
Exemplary driver circuits are disclosed in U.S. Pat. No. 5,666,078 to Lamphier et al. entitled "Programmable Impedance Output Driver" and in an article by T. J. Gabara et al. entitled "Digitally Adjustable Resistors in CMOS for High-Performance Applications", IEEE Journal of Solid-State Circuits, Vol. 27, No. 8, pp. 1176-1185 (1992). U.S. Pat. No. 5,254,883 to Horowitz et al. entitled "Electrical Current Source for a Bus" also discloses the use of an external resistor to control the impedance of an on-chip driver.
In particular, the '078 patent discloses an output driver circuit which includes an external resistance device, a voltage comparator device, control logic, an evaluate circuit and an off-chip driver circuit. A first voltage from the external resistance device is compared with a second voltage generated by the evaluate circuit. The voltage comparator device then indicates to the control logic whether the voltage generated by the evaluate circuit is greater than or less than the voltage from the external resistance device. The control logic then adjusts the evaluate circuit with a digital count until the first and second voltages are basically equal (i.e., the count is alternating between two adjacent binary count values). The control logic then sets the output driver circuit to a resistance corresponding to the lower of the two count values, to thereby produce a proper driving impedance. The Gabara et al. article also discloses a series-terminated transmission line driver circuit at FIG. 3 which uses digitally controlled pull-up and pull-down MOS resistors formed from binary-weighted transistor widths. In addition, FIG. 4 of the Gabara et al. article discloses a lower transistor array reference circuit which uses an external off-chip fixed resistor R.sub.1 and two on-chip silicide resistors R.sub.2 and R.sub.3 to generate a plurality of low control signals L0-L5. These low control signals digitally set the value of the pull-down MOS resistor. FIG. 9 of the Gabara et al. article also discloses an upper transistor array which does not use an external off-chip fixed resistor but, instead, uses the low control signals L0-L5 generated by the lower transistor array reference circuit of FIG. 4 to establish a proper value of the pull-up MOS resistor.
Referring now to FIGS. 1A-1C, 2-3 and 7, a conventional driver circuit which uses a single off-chip variable resistor to provide impedance control will be described. In particular, FIG. 1A is a block diagram of a driver circuit which includes an off-chip driver 130 for driving a transmission line having a characteristic impedance Z0=ZQ. Here, the off-chip driver 130 drives an output DQ with a logic 1 or logic 0 potential which corresponds to a differential data signal DATA/DATAB. This differential data signal may be generated by a pair of differential bit lines in an SRAM memory device, for example. As illustrated in detail by FIG. 3, the off-chip driver 130 includes a plurality of NMOS pull-up transistors PUT1-PUT6 which are connected in parallel between a first reference potential VDDQ and the output DQ and a plurality of NMOS pull-down transistors PDT1.noteq.PDT6 which are connected in parallel between a second reference potential VSSQ and the output DQ. Each of the pull-up transistors PUT1-PUT6 has a gate electrode which is responsive to a respective impedance control pull-up signal (i.e., DOU1-DOU5 and DOUS) and each of the pull-down transistors PDT1-PDT6 has a gate electrode which is responsive to a respective impedance control pull-down signal (i.e., DOD1-DOD5 and DODS). As will be understood by those skilled in the art, a digitally adjustable pull-up (or pull-down) impedance is formed by the transistor array PUT1-PUT5 consisting of five MOS transistors which are each controlled by a digital signal. The width of each of the five transistors may be selected so that the least significant impedance control pull-up signal DOU1 enables the device with width 2.sup.0 W.sub.ref while the most significant impedance control pull-up signal DOUS enables the device with width 2.sup.4 W.sub.ref. Thus, the impedance control pull-up signals PUT1-PUT5 can be used to dynamically adjust the width of the combined transistor array.
Referring again to FIG. 1A, these impedance control pull-up and pull-down signals DOUx and DODx are generated by a conventional output buffer 120 which receives a differential data signal DATA/DATAB and the multi-bit output DZQx of a ZQ driver 110 which, as illustrated best by FIG. 7, is responsive to an output enable control signal HIZs and a multi-bit count signal CTQx. A conventional output buffer 120 is illustrated by FIG. 1C. A single bit of the count signal CTQx may be denoted as CTQi and a single bit of the output DZQx may be denoted as DZQi. Thus, for each bit of the count signal CTQx, the ZQ driver 110 includes a plurality of inverters (I1-I4) and a pair of NMOS pull-down transistors N1-N2 and a pair of PMOS pull-up transistors P1-P2 which are connected in series as a CMOS inverter. As will be understood by those skilled in the art, whenever the output enable control signal HIZs is set to a logic 0 potential, the output of the CMOS inverter will be held in a high impedance state and the output DZQi will be latched at a level which is the logical complement of the state of the output of the CMOS inverter just prior to entering the high impedance state.
The multi-bit count signal CTQx is generated by a ZQ counter 160 which is responsive to an internal clock and signal UDZQ. Signal UDZQ (count-up/count-down command signal) is generated by a ZQ comparator 150 of conventional design, as illustrated by FIG. 1B. The ZQ comparator 150 is also responsive to the internal clock. The multi-bit count signal CTQx is also fed back to a ZQ detector 140 which generates a reference voltage REFIO. As explained more fully hereinbelow with respect to FIG. 2, this reference voltage REFIO varies in response to the multi-bit count signal CTQx. Moreover, this reference voltage REFIO is compared to the potential which appears across an off-chip variable resistor 170 (having a resistance RQ) at pad ZQPAD. In particular, the comparator 150 controls the level of the UDZQ signal. The level of the UDZQ signal can be varied up or down by the comparator 150 depending on whether the reference voltage REFIO is greater than or less than the potential at pad ZQPAD. For example, a logic 0 UDZQ signal may be generated if REFIO&gt;ZQPAD and a logic 1 UDZQ signal may be generated if REFIO&lt;ZQPAD. The counter 160 also counts up or counts down and thereby varies the count signal CTQx in response to the level of the UDZQ signal.
Referring now to FIG. 2, the ZQ detector 140 includes a plurality of NMOS pull-down transistors PD1-PD6 which are responsive to the multi-bit count signal CTQx (e.g., CTQ1-CTQ5). A pair of PMOS pull-up transistors PU1 and PU2 are also provided to pull up pad ZQPAD and output node REFIO. As will be understood by those skilled in the art, the potential of pad ZQPAD will vary as the resistance of the off-chip variable resistor 170 is varied and the potential of output node REFIO will vary as the combined parallel resistance of NMOS pull-down transistors PD1-PD6 is varied in response to the multi-bit count signal CTQx. Moreover, the comparator 150 and counter 160 are configured so that any variation of the off-chip variable resistor 170 to a particular resistance value will result in the generation of a corresponding multi-bit count signal CTQx. This corresponding count signal CTQx will act to turn on one or more of the NMOS pull-down transistors PD1-PD6 so that the potential of output node REFIO can be adjusted to a potential which is essentially equal to the potential of pad ZQPAD. The ZQ driver 110 and output buffer 120 will then convert the corresponding count signal CTQx to a respective impedance control pull-up signal (i.e., DOU1-DOU5 and DOUS) or a respective impedance control pull-down signal (i.e., DOD1-DOD5 and DODS), depending on the value of the differential data signal DATA/DATAB. In this manner, the effective pull-up impedance or pull-down impedance of the off-chip driver 130 can be adjusted to match the characteristic impedance Z0 of the load. Unfortunately, the pull-up impedance established by the NMOS pull-up transistors PUT1-PUT6 of FIG. 3 may become unstable. This instability may be caused by parasitic back-bias effects that result when the source terminals of these NMOS pull-up transistors are pulled up to a positive potential (shown as VDDQ) relative to their respective substrate connections. The use of NMOS pull-up transistors may also lead to impedance instability if the power supply potential (VDD&gt;VDDQ) is reduced to below about 2.5 volts.
Thus, notwithstanding these above-described off-chip driver circuits, there continues to be a need for improved off-chip driver circuits which provide accurate and stable pull-up and pull-down impedance control.